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15 Open 64 Closed
15 Open 64 Closed
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👍 👎 😄 🎉 😕 ❤️ 🚀 👀
axi_xbar synthesized？
#229 opened Apr 22, 2022 by menglinhan
Support Xilinx Vivado Simulator
#226 opened Apr 4, 2022 by skokvermon
7
There is a doc and docs folder
#215 opened Mar 8, 2022 by bluewww
Width of user-defined signaling: Extend from single parameter
#199 opened Jan 25, 2022 by andreaskurth
1
Combinatorial path from valid to ready
#195 opened Jan 10, 2022 by Realhssuperman
6
Problem with AXI Upsizer and Xilinx DDR4 Controller
#194 opened Jan 5, 2022 by luca-valente
11
Add AXI FIFO enhancement good first issue
#191 opened Dec 8, 2021 by andreaskurth
Compilation errors in axi_test in Cadence Xcellium 20.09
#186 opened Oct 9, 2021 by wirebond
1
question about hit miss unit in last level cache question
#176 opened May 30, 2021 by bufans
4
axi_xbar: Change default master port setting from input to parameter
#170 opened Apr 20, 2021 by andreaskurth
3
Replace assignments between AXI structs with calls to macros
#165 opened Feb 2, 2021 by andreaskurth v1.0
Replace axi_cut and axi_multicut by a single pipeline module
#154 opened Jan 20, 2021 by andreaskurth v1.0
Harmonize ports and parameters draft
#153 opened Jan 20, 2021 by andreaskurth v1.0
13
axi_dw_downsizer: Support for FIXED bursts
#107 opened May 11, 2020 by suehtamacv Backlog
@suehtamacv
Performance Monitor
#12 opened May 24, 2019 by andreaskurth
1 task
Backlog
@andreaskurth
ProTip! no:milestone will show everything without a milestone.